Advancements in wireless communication technology have greatly increased the versatility of today's wireless communication devices. These advancements have enabled wireless communication devices to evolve from simple mobile telephones and pagers into sophisticated computing devices capable of a wide variety of functionality such as multimedia recording and playback, event scheduling, word processing, e-commerce, etc. Further, wireless transceivers that once required large, unwieldy circuitry can now be implemented within a single, compact integrated circuit (IC) or semiconductor chip, enabling communication via many different radio access technologies (RATs) from a single device.
A power management integrated circuit (PMIC) is utilized in wireless communication devices to drive a reference clock signal generated by a crystal oscillator (XO) associated with the PMIC. Alternatively, the XO may drive the reference clock signal directly. The reference clock signal is referred to as an XO signal. The XO signal is provided from a buffer at the PMIC (or the XO itself, in the case of a directly driven XO signal) and received at an XO buffer at one or more ICs coupled to the PMIC.
A wireless communication device may employ a multichip configuration, in which there are two or more ICs that have an XO input buffer connected to the same off-chip XO driver at the PMIC. When an IC is in active operation, the XO input buffer of the IC conveys the XO input signal obtained from the PMIC to other components of the IC, such as a phase-locked loop (PLL) utilized for demodulation, frequency synthesis or other processing of wireless signals. Alternatively, an IC can be placed in an inactive mode whereby it does not utilize the XO input signal. When the XO input buffer at an IC is transitioned from the active mode to the inactive mode, or vice versa, the transition causes a change in the impedance of the buffer. This impedance change alters the input impedance seen by the PMIC buffer and, as a result, causes changes to the phase and/or delay of the XO input signal provided to each of the connected ICs.